Powering FPGAs is a giant problem. Here is help. – EEJournal


When I started working for an FPGA company ten years ago, I was amazed to find out how many power rails these parts required. I had never come across chips requiring five to ten power rails (or more). Even back then, PMOS chips only needed three supply voltages, and for a few lucky decades, 5 volts was all you needed for a power supply. Somehow, someone gave FPGA designers permission to go wild with their exaggerated power supply requirements. This unfortunate feature is not unique to single-vendor FPGAs. These days, almost all FPGAs, except the oldest and simplest ones, are like this.

For years, FPGA vendors have worked with power management integrated circuit (PMIC) chip makers to develop reference designs of power subsystems that provide all of the myriad power rails required for their FPGAs. You may have noticed that FPGA vendors tend to prefer PMIC vendors that share the same electronics vendor with the FPGA vendor, so there’s a good chance that if you prefer an FPGA from a vendor , and that most engineers have taken sides in the FPGA Thanks to the EDA tool lock, you may not find a power subsystem reference design for this chip-based FPGA from your vendor Preferred PMIC. If you are using FPGAs from multiple vendors, you may not be able to use the same PMICs to power the different brands of FPGAs, at least not using the vendor reference designs. You may need to design your own power subsystems or ask your preferred PMIC supplier to design something for you.

Now there is another alternative. It comes from a somewhat obscure programmable analog semiconductor company called AnDAPT. (Yes, indeed, that’s how the company capitalizes its name.) AnDAPT was founded by Kapil Shankar, who previously founded and was CEO of FPGA vendor SiliconBlue. (Shankar apparently likes company names with weird capitals.) Lattice Semiconductor eventually bought SiliconBlue, and Shankar’s new venture, AnDAPT, focuses on programmable analog ICs.

While rare, AnDAPT isn’t the first programmable analog device company I’ve come across. The first company I remember trying programmable analog components was International Microelectronics Products (IMP) in San Jose, California. This company’s Electrically Programmable Analog Circuits (EPACs) – called “analog FPGAs” – attempted to replace gelled analog semiconductors like op-amps and comparators, and discrete passive devices, including resistors and capacitors, by programmable semiconductors.

There isn’t much information on the web about IMP because the company went bankrupt just before the internet exploded. However, I found an obiter dictum on IMP made by David Laws – who worked as vice president of marketing at Altera in its early days, as president of QuickLogic for four years, and who has consulted with the semi- drivers for decades – during a 2012 panel discussion of AMD’s development of the 22V10 PAL which he moderated for the Computer History Museum:

“I consulted IMP on a programmable analog device. They could build a neat, custom op amp for about five bucks. Unfortunately, with off-the-shelf devices selling for 10 cents, that didn’t go very far. But it was an interesting technological exercise.

Most MBAs will tell you that an “interesting exercise in technology” isn’t a great foundation for building a financially successful business and, as David Laws explains in a separate oral history with the University of Stanford, people loved EPACs, but not enough people. bought them in volume. IMP continued as a specialty foundry, was bought out, and eventually ceased operations.

Based on this story, AnDAPT could have an uphill battle on its hands. But I think the company may have found the right niche for success: powering FPGAs from major FPGA vendors. AnDAPT’s Adaptive Multi-Rail Power Platform (AmP) PMICs are SRAM-based programmable power devices that seem just the ticket to generating lots of FPGA power rails. AmP PMICs integrate programmable power switching regulators and linear regulators as well as analog comparators, amplifiers, and power FETs into their programmable analog fabric. They also include a certain amount of programmable logic in a digital structure that includes the more familiar LUTs and RAMs, which are used for decision making and sequencing.

As mentioned above, modern FPGAs require multiple power rails. Some of these rails must supply high currents – tens of amperes – and some require relatively low currents. High-current power rails are typically implemented as switched-mode power supplies, for greater efficiency, and low-current rails typically use linear pass-through regulators, for lower cost and simplicity. So there is a mix of supply voltages and currents to deal with when designing a power supply subsystem for an FPGA.

For example, here is the power board required by an AMD-Xilinx Zynq UltraScale+ MPSoC, a SoC that combines an FPGA with a processor-based SoC:

As the graph shows, the Zynq UltraScale+ MPSoC requires ten unique power rails, represented by bubbles numbered 1 through 10. However, the complexity associated with powering a device such as the Zynq UltraScale+ MPSoC goes beyond beyond the required voltages and currents. Power rails must be initialized in the correct order and with the correct timing when the system powers up and may also need to be properly sequenced when power is removed. Violating power rail sequencing and timing specifications can destroy these types of devices. This means that designing power subsystems for these types of devices is partly an analog exercise and partly a digital exercise.

To be fair, all FPGA vendors realize the kind of power supply design challenges that they’ve dropped in the lap of system developers who want to use an FPGA, and they’ve worked with PMIC vendors to develop canned food subsystem designs that meet the requirements. of their programmable logic devices. According to AnDAPT CEO Bill McLean, FPGA vendors have done a good job developing PMIC-based solutions for power subsystems operating from 5-volt intermediate power rails.

However, some FPGA-based system designs use 12-volt intermediate power rails, and AnDAPT has discovered that this niche is not well served by existing PMIC-based solutions. The company has decided to assert its position in this 12-volt niche. To this end, AnDAPT has developed canned power subsystem designs for a growing number of programmable logic devices from AMD-Xilinx and Microchip.

For example, the company designed a two-chip power subsystem design for the Zynq UltraScale+ MPSoC based on the company’s AmP ICs, as shown in the table below:

The two AmP PMICs used for this power subsystem design, labeled ARD_X_ZUM_C1_IC1 and ARD_X_ZUM_C1_IC2 in the last column of the table, are the same basic AmP device, but they have been programmed differently to generate different power rails. PMIC configuration occurs at power-up, just like other SRAM-based programmable logic devices. AmP PMICs load their configuration onto an SPI (serial peripheral interface) port, either by acting as an SPI master and loading the configuration bit stream from a serial EEPROM, or by acting as an SPI slave and accepting a configuration bit stream from an external controller. (Note: If you are offended by the use of SPI master/slave notation, I apologize and have some empathy, but these are the official names of the SPI standard.)

What the table above does not show is that these AmP PMIC-based power subsystem designs also require external inductors, capacitors, and diodes. However, you would expect this because these power components are not easily integrated into a chip. It’s much the same when using most PMICs from other vendors. AnDAPT’s canned power subsystem designs and its design tools provide specifications for these external components as part of the downloadable design file package that the tools generate.

To carve out this 12-volt niche, AnDAPT has developed reference power subsystem designs for several AMD-Xilinx and Microchip FPGAs. AMD-Xilinx FPGAs covered include the Zynq UltraScale+ MPSoC and RFSoC families, and the original Zynq-7000 SoC family; the Kintex UltraScale+, UltraScale, and Kintex-7 FPGA families; and the Artix UltraScale+ and Artix-7 FPGA families. The company plans to develop designs for the AMD-Xilinx Virtex and Spartan-7 FPGA families and Versal ACAP families later this year. AnDAPT has also developed reference designs for Microchip PolarFire FPGAs.

You can modify these power subsystem designs or create your own design from scratch using AnDAPT’s web-based EDA tools. These tools use a simple, graphical, drag-and-drop user interface, and from the demo videos I’ve watched on the AnDAPT website, you can probably design a power subsystem with these tools. in less time than it takes for lunch, and without knowing Verilog or VHDL.

So, if your designs include the need for multiple precision power subsystems operating from intermediate 12-volt power rails, and you don’t have a solution at hand, you might want to take a look at the AmP PMICs from AnDAPT.


Advanced Micro Devices (AMD) 22V10 Programmable Array Logic (PAL) Development Team Oral History Panel

Interview with David Laws, 07 June 2013”, Silicon Genesis, Oral Histories of Semiconductor Technology, Stanford University

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